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67篇 您的检索式：期刊名="IET Computer Digital Techniques"

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	题名	作者	年代	出处	被引量
1	Reconfigurable broadcast scan compression using relaxation based test vector decomposition显示文摘	EL-MALEH A H ALI M I AL-YAMANI A A	2009	IET Computers & Digital Techniques2009，3，2：	1
2	Design and implementation challenges for adoption of the EEE 1500 stan- dard 显示文摘	HIGGINS M MACNAMEE C MULLANE B	2010	IET Computers & Digital Techniques2010，4，1：	1
3	Manipulation and optimisation techniques for Boolean logic显示文摘	A1Jassani B A Urquhart N Almaini A E A	2010	IET Computers & Digital Techniques2010，4，3：	1
4	Test data compression for system-on- a-chip using extended frequency- directed run-length eode显示文摘	EL-MALEH A H	2008	IET Computers & Digital Techniques2008，，2：	1
5	Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems显示文摘	Liu Q Constantinides G A Masselos K	2009	IET Computers & Digital Techniques2009，3，4：	1
6	Test Data Compression for System-On-A-Chip Using Extended Frequency-Directed Run-Length Code 显示文摘	A H El-Maleh	2008	IET Computers & Digital Techniques (S1751-8601)2008，2，3：	1
7	Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware显示文摘	Wang Jin Chen Qiaosong Lee C H	2008	IET Computers & Digital Techniques2008，2，5：	1
8	Manipulation and optimisation techniques for Boolean logic 显示文摘	A1 Jassani B A Urquhart N and Almaini A E A	2010	IET Computers & Digital Techniques2010，4，3：	1
9	Test data compression for system-on-a- chip using extended frequency-directed run-length code 显示文摘	EL-MALEH A H	2008	IET Computers & Digital Techniques2008，2，3：	1
10	Low-power algorithm for automatic topology generation for application-specific networks on chips显示文摘	Chang K C Chen T F	2008	IET Computers & Digital Techniques2008，2，3：	1
11	Manipulation and optimisation techniques for Boolean logic 显示文摘	B A AI Jassani N Urquhart A E A Almaini	2010	IET Computers and Digital Techniques2010，4，3：	1
12	Energy efficient i-cache using multi- ple line buffers with prediction显示文摘	Ali K Aboelaze M Datta S	2008	IET Computers & Digital Techniques2008，2，5：	1
13	Design and imple- mentation of a virtual reconfigurable architecture for dif- ferent applications of intrinsic evolvable hardware 显示文摘	Wang Jin Chen Qiaosong Lee C H	2008	IET Computers and Digital Techniques2008，2，5：	1
14	Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles显示文摘	Hosseinabady M Nunez-Yanez J L	2012	IET Computers & Digital Techniques2012，6，1：	1
15	Analysis of Shared-linkAXI显示文摘	Chang N Y C Liao Yingze Chang T S	2009	IET Computers&Digital Techniques2009，3，4：	1
16	Comparison of network-on-chip mapping algorithms targeting low energy consumption显示文摘	MARCON C AM MORENO E I CALAZAblS N L V	2008	IET Computers & Digital Techniques2008，2，6：	1
17	Test Data Compression for System - on - a - chip Using Extended Frequency - directed Run - length code 显示文摘	A H El - Maleh	2008	IET Computers & Digital Techniques2008，2，3：	1
18	Test data compression for system-on-achip using extended frequency-directed run-length code显示文摘	A H El-Maleh	2008	IET Computers and Digital Techniques2008，2，3：	1
19	Fast and memory-efficient invariant computation of ordinary Petri nets显示文摘	Law C F Gwee B H Chang J S	2007	IET Computers & Digital Techniques2007，1，5：	1
20	Very low speedperformance of active flux based sensorless control:Interior permanentmagnet synchronous motor vector control versus direct torque and fluxcontrol显示文摘	Paicu M C Boldea I Andreescu G D Blaabjerg F	2009	IET Computers and Digital Techniques2009，3，6：	1

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