DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

查看全文 作　　者：Wang Pengjun Yu [1]Junjun

机构地区：[1]Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China

出　　处：《Journal of Electronics(China)》索引2007年第24卷第2期,共7页

基　　金：Supported by the National Natural Science Foundation of China (No. 60273093);the Natural Science Foundation of Zhejinag Province(No. Y104135); the Student Sci-entific Research Foundation of Ningbo university (No.C38). 摘　　要：First the research is conducted on the design of the two-phase sinusoidal power clock gen- erator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks—Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor (NMOS) and Complementary Metal Oxide Semiconductor (CMOS) latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company (TSMC) 0.25μm CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic (BCRL) and Pass-transistor Adiabatic Logic (PAL) including their clock generators is simulated. The simula-tion result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption. 关键词：两相正弦功率时钟时钟发生器电路设计钟控传输门绝热逻辑电路

相关文献

参考文献（4）
引证文献（5）
耦合文献（41）

参考文献(4)

引证文献(5)

耦合文献(41)

互联网出版许可证新出网证(渝)字10号全国400电话 - 免长途话费

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

参考文献(4)

引证文献(5)

耦合文献(41)

用户提示