Si nanowire FET and its modeling

查看全文 作　　者：IWAI [1,2]Hiroshi;NATORI [1]Kenji;SHIRAISHI [3,4]Kenji;IWATA Jun-[4]ichi;OSHIYAMA [5]Atsushi;YAMADA [3]Keisaku;OHMORI [3]Kenji;KAKUSHIMA [2]Kuniyuki;AHMET [2]Parhat

机构地区：[1]Frontier Research Center, Tokyo Institute of Technology, Yokohama, Japan;[2]Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama, Japan;[3]Graduate School of Pure and Applied Sciences, University of Tsukuba, Tsukuba, Japan;[4]Center for Computational Sciences, University of Tsukuba, Tsukuba, Japan;[5]School of Engineering, The University of Tokyo, Tokyo, Japan

出　　处：《Science China(Information Sciences)》索引2011年第54卷第5期,共8页

基　　金：supported by the NEOD's (New Energy and Industrial Technology Development Organization) program for the 'Development of Nanoelectronic Device Technology' 摘　　要：Because of its ability to effectively suppress off-leakage current with its gate-around conffguration, the Si nanowire FET is considered to be the ultimate structure for ultra-small CMOS devices to the extent that the devices would be approaching their downsized limits. Recently, several experimental studies of Si nanowire FETs with on-currents much larger than those of planar MOSFETs have been published. Consequently, Si nanowire FETs are now gaining significant attention as the most promising candidate for mainstream CMOS devices in the 2020s. To enable the introduction of the Si nanowire FETs into integrated circuits, good compact models, which circuit designers can easily handle, are essential. However, it is a very challenging task to establish such a compact model, because the ID - VD characteristics of Si nanowire FETs are affected by the band structure of the nanowire, which is very sensitive to the nanowire diameter, cross-sectional shape, crystal orientation, mechanical stress and interface states. In this paper, the recent status of research on Si nanowire FETs in experimental and theoretical studies is described. 关键词：硅纳米线场效应管 CMOS器件场效应晶体管硅集成电路建模 MOSFET 设计人员

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Si nanowire FET and its modeling

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