A 14b 250MSps Pipelined ADC with Digital Self-calibration in 0.18μm CMOS Process

查看全文 作　　者：LIU [1]Haitao;WU [1]Junjie;ZHANG [1]Lizheng;DENG [1]Qing;SUN [1]Jie

机构地区：[1]Nanjing Research Institute of Electronics Technology, Nanjing 210000, China

出　　处：《Chinese Journal of Electronics》索引2018年第27卷第3期,共5页

摘　　要：A 14-bit pipelined Analog-to-digital converter(ADC) with a single-side digital self-calibration in a 0.18μm CMOS process is presented. The single-side foreground digital self-calibration is introduced to reduce the nonlinearity caused by capacitor mismatches. The ADC has a front-end Sample-and-hold(SH) circuit, followed by 13 1.5 bit/stage sub-ADC and 2 bit flash ADC at last. Test results show that, with a 140 MHz input and 200 MHz sampling rate, the SIAND is improved from 59 dB to 66 dB and SFDR is improved from 62 dBc to 82 dBc with the digital calibration. The measured SFDR reaches 77 dBc even at 250 MSps after calibration. The total power dissipation is 398 mW at 250 MSps including the parallel Low voltage differential signal(LVDS) output drivers. 关键词：互补金属氧化物半导体模数转换器刻度 SFDR MSPS dBc 微分信号变换器

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A 14b 250MSps Pipelined ADC with Digital Self-calibration in 0.18μm CMOS Process

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