A TSE based design for MMSE and QRD of MIMO systems based on ASIP

查看全文 作　　者：[1,2,3]冯雪林;SHI [1]Jinglin;CHEN [1]Yang;FU [3]Yanlu;ZHANG [1]Qineng;XIAO [3]Feng 机构地区：[1]Beijing Key Laboratory of Mobile Computing and Pervasive Device,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100080,P.R.China;[2]School of Computer Science and Technology,University of Chinese Academy of Sciences,Beijing 100049,P.R.China;[3]Beijing Sylincom Technology Co.,Ltd.,Beijing 100190,P.R.China 出　　处：《High Technology Letters》索引2023年第29卷第2期,共8页 基　　金：Supported by the Industrial Internet Innovation and Development Project of Ministry of Industry and Information Technology (No.GHBJ2004)。 摘　　要：A Taylor series expansion(TSE) based design for minimum mean-square error(MMSE) and QR decomposition(QRD) of multi-input and multi-output(MIMO) systems is proposed based on application specific instruction set processor(ASIP), which uses TSE algorithm instead of resource-consuming reciprocal and reciprocal square root(RSR) operations.The aim is to give a high performance implementation for MMSE and QRD in one programmable platform simultaneously.Furthermore, instruction set architecture(ISA) and the allocation of data paths in single instruction multiple data-very long instruction word(SIMD-VLIW) architecture are provided, offering more data parallelism and instruction parallelism for different dimension matrices and operation types.Meanwhile, multiple level numerical precision can be achieved with flexible table size and expansion order in TSE ISA.The ASIP has been implemented to a 28 nm CMOS process and frequency reaches 800 MHz.Experimental results show that the proposed design provides perfect numerical precision within the fixed bit-width of the ASIP, higher matrix processing rate better than the requirements of 5G system and more rate-area efficiency comparable with ASIC implementations. 关 键 词：multi-input and multi-output(MIMO) minimum mean-square error(MMSE) QR decomposition(QRD) Taylor series expansion(TSE) application specific instruction set processor(ASIP) instruction set architecture(ISA) single instruction multiple data(SIMD) very long instruction word(VLIW)