Analytical delay models for RLC interconnects under ramp input

查看全文 作　　者：REN [1]Yinglei;MAO [1]Junfa;LI [1]Xiaochun 机构地区：[1]Department of Electronic Engineering,Shanghai Jiao Tong University,Shanghai 200030,China 出　　处：《Frontiers of Electrical and Electronic Engineering in China》索引2007年第2卷第1期,共4页 基　　金：supported by National Science Fund for Creative Research Groups(No.60521002);the Grant of Doctoral Research Foundation from Ministry of Education,China(No.20040248034). 摘　　要：Analytical delay models for Resistance Inductance Capacitance(RLC)interconnects with ramp input are presented for different situations,which include overdamped,underdamped and critical response cases.The errors of delay estimation using the analytical models proposed in this paper are less by 3%in comparison to the SPICE-computed delay.These models are meaningful for the delay analysis of actual circuits in which the input signal is ramp but not ideal step input. 关 键 词：ramp input DELAY RLC interconnect model analytical formula