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您的检索式：作者名="David Z.Pan"
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| 1 | Design for manufacturability and reliability in extreme-scaling VLSI显示文摘In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14 nm nanometer regime, modern integrated circuit(IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI. | Bei YU Xiaoqing XU Subhendu ROY Yibo LIN Jiaojiao OU David Z.PAN | 2016 | Science China(Information Sciences)2016，59，6： | 1 |
| 2 | Generative Learning in VLSI Design for Manufacturability: Current Status and Future Directions显示文摘With the continuous scaling of integrated circuit technologies,design for manufacturability(DFM)is becoming more critical,yet more challenging.Alongside,recent advances in machine learning have provided a new computing paradigm with promising applications in VLSI manufacturability.In particular,generative learning-regarded among the most interesting ideas in present-day machine learning-has demonstrated impressive capabilities in a wide range of applications.This paper surveys recent results of using generative learning in VLSI manufacturing modeling and optimization.Specifically,we examine the unique features of generative learning that have been leveraged to improve DFM efficiency in an unprecedented way;hence,paving the way to a new data-driven DFM approach.The state-of-the-art methods are presented,and challenges/opportunities are discussed. | Mohamed Baker Alawieh Yibo Lin Wei Ye David Z.Pan | 2019 | Journal of Microelectronic Manufacturing2019，2，4： | 0 |
| 3 | Challenges and opportunities toward fully automated analog layout design显示文摘Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout automation,analog IC layout design is still heavily manual,which leads to a more time-consuming and error-prone process.In recent years,significant progress has been made in automated analog layout design with emerging of several open-source frameworks.This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges.We then present recent research trends and opportunities in the field.Finally,we summaries the paper with open questions and future directions for fully-automating the analog IC layout. | Hao Chen Mingjie Liu Xiyuan Tang Keren Zhu Nan Sun David Z.Pan | 2020 | Journal of Semiconductors2020，41，11： | 0 |
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