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| 1 | Inhibition of FOXO3a/BIM signaling pathway contributes to the protective effect of salvianolic acid A against cerebral ischemia/reperfusion injury显示文摘Salvianolic acid A(SalA) is an effective compound extracted from traditional Chinese medicine Salvia miltiorrhiza Bunge. The Forkhead box O3a(FOXO3a) signaling pathway plays crucial roles in the modulation of ischemia-induced cell apoptosis. However, no information about the regulatory effect of SalA on FoxO3a is available. To explore the anti-cerebral ischemia effect and clarify the therapeutic mechanism of SalA, SH-SY5Y cells and Sprague–Dawley rats were applied, which were exposed to oxygen glucose deprivation/reoxygenation(OGD/R) and middle cerebral artery occlusion/reperfusion(MCAO/R) injuries, respectively. The involved pathway was identified using the specific inhibitor LY294002. Results showed that SalA concentration-dependently inhibited OGD/R injury triggered cell viability loss. SalA reduced cerebral infarction, lowered brain edema, improved neurological function, and inhibited neuron apoptosis in MCAO/R rats, which were attenuated by the treatment of phosphatidylinositol-4,5-bisphosphate 3-kinase(PI3K) specific inhibitor LY294002. SalA time-and concentration-dependently upregulated the phosphorylation levels of protein kinase B(AKT) and its downstream protein FOXO3a. Moreover, the nuclear translocation of FOXO3a was inhibited by SalA both in vivo and in vitro, which was also reversed by LY294002. The above results indicated that SalA fought against ischemia/reperfusion damage at least partially via the AKT/FOXO3a/BIM pathway. | Junke Song Wen Zhang Jinhua Wang Haiguang Yang Qimeng Zhou Haigang Wang Li Li Guanhua Du | 2019 | Acta Pharmaceutica Sinica B2019，9，3： | 20 |
| 2 | REVIEW OF ADVANCED FPGA ARCHITECTURES AND TECHNOLOGIES显示文摘Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development. | Yang Haigang Zhang Jia Sun Jiabin Yu Le | 2014 | Journal of Electronics(China)2014，31，5： | 6 |
| 3 | Investigation of gas-solids flow hydrodynamics in a cold model of a dual fluidised bed gasifier using electrical capacitance tomography sensors显示文摘The flow characteristics of a dual fluidised bed gasifier(DFBG)are more complex than those of a single fluidised bed gasifier.For stable operation and appropriate control,a cold DFBG test facility with both an upper and a lower U-valve was built,and electrical capacitance tomography(ECT)sensors were installed with pressure transducers to investigate the effects of operating conditions on gas-solids flow hydrodynamics.The operating parameters included gas velocities in the riser and in the bubbling fluidised bed,aeration velocity in the lower U-valve,bed material inventory,and particle size.This is the first time that ECT was applied in different flow zones of a dual fluidised bed gasifier system.The experimental results indicated that ECT in the recycle chamber could monitor the performance of the lower U-valve under different operating conditions for early detection of gas shortcut from the riser to the bubbling bed.Three main flow regimes in the riser and the differences between the reactors were identified by two sets of ECT sensors with pressure transducers.Finally,the effects of the operating conditions on the pressure drop in different parts of the DFBG was investigated. | Zhan Luo Yonglei Lin Qiuya Tu Wuqiang Yang Haigang Wang | 2020 | Particuology2020，18，4： | 4 |
| 4 | OsPKpa_1 encodes a plastidic pyruvate kinase that affects starch biosynthesis in the rice endosperm显示文摘Pyruvate kinase(PK) is a key enzyme in glycolysis and carbon metabolism. Here, we isolated a rice(Oryza sativa) mutant, w59, with a white-core floury endosperm. Map-based cloning of w59 identified a mutation in OsPKpa_1, which encodes a plastidic isoform of PK(PKp). OsPKpa_1 localizes to the amyloplast stroma in the developing endosperm, and the mutation of OsPKpa_1 in w59 decreases the plastidic PK activity, resulting in dramatic changes to the lipid biosynthesis in seeds. The w59 grains were also characterized by a marked decrease in starch content. Consistent with a decrease in number and size of the w59 amyloplasts, large empty spaces were observed in the central region of the w59 endosperm, atthe early grain-filling stage. Moreover, a phylogenetic analysis revealed four potential rice isoforms of OsPKp. We validated the in vitro PK activity of these OsPKps through reconstituting active PKp complexes derived from inactive individual OsPKps, revealing the heteromeric structure of rice PKps, which was further confirmed using a protein–protein interaction analysis. These findings suggest a functional connection between lipid and starch synthesis in rice endosperm amyloplasts. | Yue Cai Wenwei Zhang Jie Jin Xiaoming Yang Xiaoman You Haigang Yan Liang Wang Jie Chen Jiahuan Xu Weiwei Chen Xingang Chen Jing Ma Xiaojie Tang Fei Kong Xiaopin Zhu Guoxiang Wang Ling Jiang William Terzaghi Chunming Wang Jianmin Wan | 2018 | Journal of Integrative Plant Biology2018，60，11： | 3 |
| 5 | In vivo volumetric monitoring of revascularization of traumatized skin using extended depth-of-field photoacoustic microscopy显示文摘Faster and better wound healing is a critical medical issue.Because the repair process of wounds is closely related to revascularization,accurate early assessment and postoperative monitoring are very important for establishing an optimal treatment plan.Herein,we present an extended depth-of-field photoacoustic microscopy system(E-DOF-PAM)that can achieve a constant spatial resolution and relatively uniform excitation efficiency over a long axial range.The superior performance of the system was verified by phantom and in vivo experiments.Furthermore,the system was applied to the imaging of normal and trauma sites of volunteers,and the experimental results accurately revealed the morphological differences between the normal and traumatized skin of the epidermis and dermis.These results demonstrated that the E-DOF-PAM is a powerful tool for observing and understanding the pathophysiology of cutaneous wound healing. | Zhongwen CHENG Haigang MA Zhiyang WANG Sihua YANG | 2020 | Frontiers of Optoelectronics2020，13，4： | 3 |
| 6 | Perfectly Matched Layer for an Elastic Parabolic Equation Model in Ocean Acoustics显示文摘The perfectly matched layer(PML) is an effective technique for truncating unbounded domains with minimal spurious reflections. A fluid parabolic equation(PE) model applying PML technique was previously used to analyze the sound propagation problem in a range-dependent waveguide(Lu and Zhu, 2007). However, Lu and Zhu only considered a standard fluid PE to demonstrate the capability of the PML and did not take improved one-way models into consideration. They applied a [1/1] Padé approximant to the parabolic equation. The higher-order PEs are more accurate than standard ones when a very large angle propagation is considered. As for range-dependent problems, the techniques to handle the vertical interface between adjacent regions are mainly energy conserving and single-scattering. In this paper, the PML technique is generalized to the higher order elastic PE, as is to the higher order fluid PE. The correction of energy conserving is used in range-dependent waveguides. Simulation is made in both acoustic cases and seismo-acoustic cases. Range-independent and range-dependent waveguides are both adopted to test the accuracy and efficiency of this method. The numerical results illustrate that a PML is much more effective than an artificial absorbing layer(ABL) both in acoustic and seismo-acoustic sound propagation modeling. | XU Chuanxiu ZHANG Haigang PIAO Shengchun YANG Shi’e SUN Sipeng TANG Jun | 2017 | Journal of Ocean University of China2017，16，1： | 3 |
| 7 | Researches on the distribution law of vector sound field in elastic wedge bottom显示文摘基于为计算健全向量的有弹性的寓言的方程方法,领域被学习了的方法。水里的向量领域和相应震波地被计算了为在有有弹性的楔底部的海洋的环境下文健全。为健全来源的不同频率和深度的健全领域分发上的效果被研究了,进底部有声能漏的结果表演,漏发生了的位置能被海洋深度的比率决定到波长,作为与正常相比模式理论。 | ZHANG Haigang PIAO Shengchun YANG Shi'e AN Xudong | 2011 | Chinese Journal of Acoustics2011，30，4： | 2 |
| 8 | A 0.18μm CMOS GAIN-SWITCHED LNA AND MIXER WITH LARGE DYNAMIC RANGE显示文摘A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier(LNA) and a passive mixer with no external balun for near-zero-IF(Intermediate Frequency)/RF(Radio Frequency) applications are described.The LNA,fabricated in the 0.18μm 1P6M CMOS technology,adopts a gain-switched technique to increase the linearity and enlarge the dynamic range.The mixer is an IQ-based passive topology.Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω.Combining LNA and mixer,the front-end measured performances in high gain state are:-15dB of S11,18.5dB of voltage gain,4.6dB of noise figure,-15dBm of ⅡP3,-85dBm to -10dBm dynamic range.The full circuit drains 6mA from a 1.8V supply. | Yang Jinlin Yang Haigang Xue Bing | 2008 | Journal of Electronics(China)2008，25，5： | 2 |
| 9 | A CMOS dynamic comparator for pipeline ADCs with improved speed/power rati o显示文摘 | Liu Ke Yang Haigang | 2008 | {H}半导体学报2008，，01： | 1 |
| 10 | A high precision CMOS weak current readout circuit显示文摘 | Wu Qisong Yang Haigang Yin Tao | | 0，，07： | 1 |
| 11 | AIR-GAP-BASED RF COAXIAL TSV AND ITS CHARACTERISTIC ANALYSIS显示文摘Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via(TSV) with operations for high-speed vertical communication.In this paper,we introduce a novel air-gap coaxial TSV that is suiTab.for such RF applications.Firstly,the detailed fabrication process is described to explain how to acquire such a structure.Then,an Resistor Inductance Conductance Capacitance(RLGC) model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV.The model is further verified by a 3D field solver program through the S-parameter comparison.With reference to the numerically simulated results,this analytical model delivers a maximum deviation of less than 6‰,on the conditions of varying diameters,outer to inner radius ratios,and SU-8 central angles,etc.Taking advantages of scalability of the model,a number of air-gap-based TSV designs are simulated,providing 1.6~4.0 times higher bandwidth than the conventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs. | Yu Le Sun Jiabin Zhang Chunhong Wang Zhaoxin Zhang Chao Yang Haigang | 2013 | Journal of Electronics(China)2013，30，6： | 1 |
| 12 | ARCHITECTURE MODEL AND RESOURCE GRAPH BUILDING ALGORITHM FOR DETAILED FPGA ARCHITECTURE DESIGN显示文摘This paper addresses the issue of designing the detailed architectures of Field-Programmable Gate Arrays(FPGAs), which has a great impact on the overall performances of an FPGA in practice. Firstly, a novel FPGA architecture description model is proposed based on an easy-to-use file format known as YAML. This format permits the description of any detailed architecture of hard blocks and channels. Then a general algorithm of building FPGA resource graph is presented. The proposed model is scalable and capable of dealing with detailed architecture design and can be used in FPGA architecture evaluation system which is developed to enable detailed architecture design. Experimental results show that a maximum of 16.36% reduction in total wirelength and a maximum of 9.34% reduction in router effort can be obtained by making very little changes to detailed architectures, which verifies the necessity and effectiveness of the proposed model. | Li Zhihua Yang Haigang Yang Liqun Li Wei Huang Juan | 2014 | Journal of Electronics(China)2014，31，6： | 1 |
| 13 | Modeling of Amperometric Immunosensor for CMOS Integration显示文摘A circuit model of the Amperometric immunosensor for use in the biosensor system-on-chip simulation is proposed in this paper.The model parameters are extracted with several methods and verified by MATLAB and SPICE simulation.A CMOS potentiostat circuit required for conditioning the Amperometric immunosensor is also included in the circuit model.The mean square error norm of the simulated curve against the measured one is 8.65×10^(-17) The whole circuit has been fabricated in a 0.35μm CMOS process. | Ce Li Haigang Yang Shanhong Xia Chao Bian | 2006 | 稀有金属材料与工程2006，35，A03： | 1 |
| 14 | The study of epoxidized rapeseed oil used as a potential biodegradable lubricant显示文摘 | Xuedong Wu Xingang Zhang Shengrong Yang Haigang Chen Dapu Wang | 2000 | Journal of the American Oil Chemists’ Society2000，，5： | 1 |
| 15 | A Full CMOS Integration Including ISFET Microsensors and Interface Circuit for Biochemical Applications显示文摘One of today's challenges is the integration of ISFETs in chemical and biochemical Microsystems.This article presents a full integration of ISFET chip containing the ISFET/REFET(reference FET) pair,ISFET/REFET amplifiers,bias current generator,as well as a reference electrode structure,all integrated on the same chip based on CMOS technology.The sensor chip was fabricated in a standard 0.35μm CMOS process(Chartered Semiconductor,Singapore).The extra post processing steps have been developed and added for depositing membranes.Finally,the pH response of the integrated sensor was measured with the interface circuit. | Jinbao Wei Haigang Yang Hongguang Sun Zengjin Lin Shanhong Xia | 2006 | 稀有金属材料与工程2006，35，A03： | 1 |
| 16 | A BFSK and OOK IF demodulation circuit with 2.8 μs settling time and re-configurable image rejection functions for MICS/BCC applications显示文摘A BFSK and OOK IF base-band circuit is provided to implement the low-IF RF receivers for a dualband MICS/BCC network controller. In order to transfer the massive vital data immediately, the IF circuit is comprised of the fast-settling feed-forward programmable gain amplifier(PGA), a G_m-C complex filter, the fixed gain amplifier(FGA) and a 4-input 'quadratic sum' demodulator. A novel auto-switched coarse gain-setting method is adopted in the PGA to enhance the reaction speed and narrow the output signal range. Also the PGA does not suffer the same stability constraint as open-loop topologies. The complex filter fulfills the function of image rejection,in which the center frequency and bandwidth can be adjusted individually. The FGA is used to ameliorate the linearity and the 'quadratic sum' demodulator can reduce the overall power consumption. The designed IF circuit is fabricated with SMIC 0.18 μm CMOS process. The chip area is about 5.36 mm^2. Measurement results are given to verify the design goals. | Tongqiang Gao Zhenxiong Chen Siqi Zhao Haigang Yang Xinxia Cai | 2018 | Journal of Semiconductors2018，39，7： | 1 |
| 17 | Efficiently Exploring FPGA Design Space Based on Semi-Supervised Learning显示文摘Design space exploration(DSE) is an important step before the physical level design of Field programmable gate arrays(FPGA). An optimum architecture is usually selected from the whole space. As the architecture parameters increase, the huge time cost to explore an exponentially increasing space makes this method unrealistic. We propose a novel predictive modeling approach called ECOMT to estimate the area and delay of a circuit which is mapped onto an FPGA with certain architecture.Semi-supervised model tree is adopted to model the performance with respect to architecture parameters. Combined with nonlinear programming, the area and delay model obtained can be used to guide the DSE. Experimental results show that the model trained through ECOMT has Mean relative error(MRE) below 5% compared to VTR.Meanwhile the time used to attain the model is less than3 minutes, which reduces the time of DSE considerably. | YANG Liqun YANG Haigang LI Wei LI Zhihua | 2016 | Chinese Journal of Electronics2016，25，1： | 1 |
| 18 | On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time显示文摘Statistics shows that over 95% of FPGA manufacturing test time is spent on loading test configuration bitstreams. Reducing the test time that spent on loading test configuration bitstreams could significantly reduce FPGA test time. A new approach which can significantly reduce the FPGA test time is presented. Experimental results show that the proposed technique can at least reduce the configuration loading time by 96%, while getting 100%test coverage with less than 1.2% hardware overhead. | WANG Fei WANG Da YANG Haigang XIE Xianghui FAN Dongrui | 2016 | Chinese Journal of Electronics2016，25，1： | 1 |
| 19 | FPGA based multi-channel variable-length FFT implementation显示文摘High-speed real-time digital frequency analysis is one major field of Fast Fourier Transform(FFT)application,such as Synthetic Aperture Radar(SAR)processing and medical imaging.In SAR processing,the image size could be 4 k×4 k in normal and it has become larger over the years.In the view of real-time,extensibility and reusable characteristics,an Field Programmable Gate Array(FPGA)based multi-channel variable-length FFT architecture which adopts radix-2 butterfly algorithm is proposed in this paper.The hardware implementation of FFT is partially reconfigurable architecture.Firstly,the proposed architecture in the paper has flexibility in terms of chip area,speed,resource utilization and power consumption.Secondly,the proposed architecture combines serial and parallel methods in its butterfly computations.Furthermore,on system-level issue,the proposed architecture takes advantage of state processing in serial mode and data processing in parallel mode.In case of sufficient FPGA resources,state processing of serial mode mentioned above is converted to pipeline mode.State processing of pipeline mode achieves high throughput. | WANG Jiawei YU Le YANG Haigang FENG Guanglang SUN Jiabin LUO Yang | 2017 | 太赫兹科学与电子信息学报2017，15，3： | 1 |
| 20 | TIMING SLACK OPTIMIZATION APPROACH USING FPGA HYBRID ROUTING STRATEGY OF RIP-UP-RETRY AND PATHFINDER显示文摘To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a collocation table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized(reduced) by 85.8% on average compared with the Versatile Place and Route(VPR) timing-driven routing algorithm, while the run-time is only increased by 15.02% on average. | Yu Wei Yang Haigang Liu Yang Huang Juan | 2014 | Journal of Electronics(China)2014，31，3： | 1 |
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