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| 1 | A Reconfigurable Block Cryptographic Processor Based on VLIW Architecture显示文摘An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the broad range of support.However,these methods could not achieve a good tradeoff between high-speed processing and flexibility.In this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block ciphers.As for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme.The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing units.It has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 MHz.and power consumption is 420 mw.Ten kinds of block and hash ciphers were realized in the processor.The encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs. | LI Wei ZENG Xiaoyang NAN Longmei CHEN Tao DAI Zibin | 2016 | China Communications2016，13，1： | 11 |
| 2 | A High Energy-Efficient Reconfigurable VLIW Symmetric Cryptographic Processor with Loop Buffer Structure and Chain Processing Mechanism显示文摘By exploring symmetric cryptographic data level and instruction-level parallelism, the reconfigurable processor architecture for symmetric ciphers is presented based on Very-long instruction word(VLIW) structure. The application-specific instruction-set system for symmetric ciphers is proposed. As for the same arithmetic operation of symmetric ciphers, eleven kinds of reconfigurable cryptographic arithmetic units are designed by the reconfigurable technology. As to the requirement of high energy-efficient design, the loop buffer structure for instruction fetching unit is proposed to reduce the power consumption significantly with the same frequency as conventional, meanwhile, the chain processing mechanism is proposed to improve the cryptographic throughput without any area overhead. It has been fabricated with 0.18μm CMOS technology. The result shows that the processor can work up to 200 MHz, and the fourteen kinds of cryptographic algorithms were mapped in the processor, the encryption throughput of AES, SNOW2.0 and SHA2 algorithm can achieve 1.19 Gbps, 1.05 Gbps, and 407 Mbps respectively. | LI Wei ZENG Xiaoyang DAI Zibin NAN Longmei CHEN Tao MA Chao | 2017 | Chinese Journal of Electronics2017，26，6： | 5 |
| 3 | Approach for earth observation satellite real-time and playback data transmission scheduling显示文摘The scheduling of earth observation satellites(EOSs)data transmission is a complex combinatorial optimization problem. Current researches mainly deal with this problem on the assumption that the data transmission mode is fixed, either playback or real-time transmission. Considering the characteristic of the problem, a multi-satellite real-time and playback data transmission scheduling model is established and a novel algorithm based on quantum discrete particle swarm optimization(QDPSO)is proposed. Furthermore, we design the longest compatible transmission chain mutation operator to enhance the performance of the algorithm. Finally, some experiments are implemented to validate correctness and practicability of the proposed algorithm. | Hao Chen Longmei Li Zhinong Zhong Jun Li | 2015 | Journal of Systems Science & Complexity2015，28，5： | 4 |
| 4 | A VLIW Architecture Stream Cryptographic Processor for Information Security显示文摘As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers. | Longmei Nan Xuan Yang Xiaoyang Zeng Wei Li Yiran Du Zibin Dai Lin Chen | 2019 | China Communications2019，16，6： | 4 |
| 5 | A scheme of hazardous chemical identification for transportation incidents显示文摘 | Longmei Chen Dahe Jiang JiyangXia | 1997 | Journal of Hazardous Materials1997，，56： | 1 |
| 6 | Effect of rare earth element yttrium addition on microstructures and properties of a 21Cr–11Ni austenitic heat-resistant stainless steel显示文摘 | Lei Chen Xiaocong Ma Longmei Wang Xiaoning Ye | 2010 | Materials and Design2010，，4： | 1 |
| 7 | An energy-efficient reconfigurable asymmetric modular cryptographic operation unit for RSA and ECC显示文摘RSA and ellipse curve cryptography(ECC)algorithms are widely used in authentication,data security,and access control.In this paper,we analyze the basic operation of the ECC and RSA algorithms and optimize their modular multiplication and modular inversion algorithms.We then propose a reconfigurable modular operation architecture,with a mix-memory unit and double multiply-accumulate structures,to realize our unified,asymmetric cryptosystem structure in an operational unit.Synthesized with 55-nm CMOS process,our design runs at 588 MHz and requires only 437801µm2 of hardware resources.Our proposed design takes 21.92 and 23.36 mW for 2048-bit RSA modular multiplication and modular inversion respectively,as well as 16.16 and 15.88 mW to complete 512-bit ECC dual-field modular multiplication and modular inversion respectively.It is more energy-efficient and flexible than existing single algorithm units.Compared with existing multiple algorithm units,our proposed method shows better performance.The operation unit is embedded in a 64-bit RISC-V processor,realizing key generation,encryption and decryption,and digital signature functions of both RSA and ECC.Our proposed design takes 0.224 and 0.153 ms for 256-bit ECC point multiplication in G(p)and G(2^(m))respectively,as well as 0.96 ms to complete 1024-bit RSA exponentiation,meeting the demand for high energy efficiency. | Mengni BIE Wei LI Tao CHEN Longmei NAN Danyang YANG | 2022 | Frontiers of Information Technology & Electronic Engineering2022，23，1： | 0 |
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