| 1 | Accelerating an FPGA-Based SAT Solver by Software and Hardware Co-design显示文摘The Boolean Satisfiability (SAT) problem is the key problem in computer theory and application. Field-programmable gate array (FPGA) has been ad-dressed frequently to accelerate the SAT solving process in the last few years owing to its parallelism and flexibility. We have proposed a novel SAT solver based on an improved local search algorithm on the reconfigurable hardware platform. The new software preprocessing procedure and hardware architecture are involved to solve large-scale SAT problems instances. As compared with the past solvers, the proposed solver has the following advantages:the preprocessing technology can strongly improve the efficiency of solver;the strategy of strengthening the variable selection can avoid the same variable flipped continuously and repeatedly. It reduces the possibility of search falling into local minima. The experimental results indicate that the solver can solve problems of up to 32K variables/128K clauses without off-chip memory banks, and has better performance than previous works. | MA Kefan XIAO Liquan ZHANG Jianmin LI Tiejun | 2019 | Chinese Journal of Electronics2019，28，5： | 3 |
| 2 | An Parallel FPGA SAT Solver Based on Multi-Thread and Pipeline显示文摘The Boolean Satisfiability(SAT) problem is the key problem in computer theory and application. A parallel multi-thread SAT solver named pprob SAT+ on a configurable hardware is proposed. In the algorithm,multithreads are executed simultaneously to hide the circuit stagnate. In order to improve the working frequency and throughput of the SAT solver, the deep pipeline strategy is adopted. When all data stored in block random access memory of the field programmable gate array, the solver can achieve maximum performance. If partial data are stored in the external memory, the size of the problem instances the SAT solver can be greatly improved. The experimental results show that the speedup of three-thread SAT solver is approximately 2.4 times with single thread,and shows that the pprob SAT+ have achieved substantial improvement while a solution is found. | LI Tiejun MA Kefan ZHANG Jianmin | 2021 | Chinese Journal of Electronics2021，30，6： | 0 |
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