2篇
您的检索式：作者名="Maoxiang YI"
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| 1 | A novel BIST scheme for circuit aging measurement of aerospace chips显示文摘The avionics working environment is bad, easy to accelerate aging of circuits. Circuit aging is one of the important factors that influence the reliability of avionics, so circuit aging testing is of great significance to improve the reliability of avionics. As continuing aging would degrade circuit performance, aging can be monitored through precise measurement of performance degradation. However, previous methods for predicting circuit performance have limited prediction accuracy. In this paper, we propose a novel Built-In Self-Test(BIST) scheme for circuit aging measurement, which constructs self-oscillation loops employing parts of critical paths and activates oscillations by specific test patterns. An aging signature counter is then used to capture the oscillation frequency and in turn measure the aging state of the circuit. We propose to implement this measurement process by BIST. Experimental results show that the proposed in-field aging measurement is robust with respect to process variations and can achieve a precision of about 90%. The application of this scheme has a certain value to improve the reliability of avionics systems. | Huaguo LIANG Xiangsheng FANG Maoxiang YI Zhengfeng HUANG Yingchun LU | 2018 | Chinese Journal of Aeronautics2018，31，7： | 3 |
| 2 | CORE-UNIFIED SOC TEST DATA COMPRESSION AND APPLICATION显示文摘The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively. | Yi Maoxiang Guo Xueying Liang Huaguo Wang Wei Zhang Lei | 2010 | Journal of Electronics(China)2010，27，1： | 0 |
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