Parallelization of intra prediction algorithm based on array processor

查看全文 作　　者：[1]朱筠;Jiang [2]Lin;Shi [3]Pengfei;Xie [3]Xiaoyan;Shen [4]Xubang

机构地区：[1]School of Microelectronics,Xidian University;[2]Xi'an University of Science and Technology;[3]School of Computer Science and Technology,Xi'an University of Posts and Telecommunications;[4]Xi'an Microelectronic Technology Research Institute

出　　处：《High Technology Letters》索引2019年第25卷第1期,共7页

基　　金：Supported by the National Natural Science Foundation of China(No.61772417,61634004,61602377,61272120);the Shaanxi Provincial Co-ordination Innovation Project of Science and Technology(No.2016KTZDGY02-04-02);the Shaanxi Provincial key R&D plan(No.2017GY-060) 摘　　要：For the characteristics of intra prediction algorithms, the data dependence and parallelism between intra prediction models are first analyzed. This paper proposes a parallelization method based on dynamic reconfigurable array processors provided by the project team, and uses data level parallel(DLP) algorithms in multi-core units. The experimental results show that Y-component of peak signal to noise ratio(Y-PSNR) is improved about 10 dB and the time is saved 63% compared with high-efficiency video coding(HEVC) test model HM10.0. This method can effectively reduce codec time of the video and reduce computational complexity. 关键词：high-efficiency VIDEO CODING (HEVC) INTRA PREDICTION PARALLELIZATION MAPPING

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Parallelization of intra prediction algorithm based on array processor

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耦合文献(9)

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