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| 1 | Design and experiment on intelligent fuzzy monitoring system for corn planters显示文摘When sowing summer corn without tillage,it is necessary to ensure that the furrow opener is free from straw congestion and that the spacing of the sowing can be adjusted according to the breeds of corn and the preset seeding rate per acre.On the basis of the structural features of newly developed no-tillage corn fertilizers,an intelligent fuzzy monitoring system for corn planters was developed in this study.The system facilitates automatic control of the spacing adjustment and the status monitor for the fertilizer tank,seed tank,and seeding orifice.According to the preset number of rows,line spacing,number of plants per acre,and seed germination rate,the control rate can be calculated through designing in surveillance software.The control rate is output to the fuzzy controller through the digital output module of the CAN bus.Fuzzy control is applied to the DC motor for stepless adjustment of the spacing.A system for video surveillance of the working status of a planter is developed for displaying a real-time video image of the planter operation and achieving an anti-congestion status monitoring of a no-tillage planting operation in a dusty environment.Through field trials,the detection accuracy was 91.4%.The seed-clogging fault-alarm accuracy was 96.0%.The entire system remained stable and reliable. | Du Ruicheng Gong Bingcai Liu Ningning Wang Chenchen Yang Zidong Ma Mingjian | 2013 | International Journal of Agricultural and Biological Engineering2013，6，3： | 16 |
| 2 | DSNNs:learning transfer from deep neural networks to spiking neural networks显示文摘Deep neural networks(DNNs)have drawn great attention as they perform the state-of-the-art results on many tasks.Compared to DNNs,spiking neural networks(SNNs),which are considered as the new generation of neural networks,fail to achieve comparable performance especially on tasks with large problem sizes.Many previous work tried to close the gap between DNNs and SNNs but used small networks on simple tasks.This work proposes a simple but effective way to construct deep spiking neural networks(DSNNs)by transferring the learned ability of DNNs to SNNs.DSNNs achieve comparable accuracy on large networks and complex datasets. | 张磊 Du Zidong Li Ling Chen Yunji | 2020 | High Technology Letters2020，26，2： | 1 |
| 3 | Assembly language and assembler for deep learning accelerators显示文摘Deep learning accelerators(DLAs)have been proved to be efficient computational devices for processing deep learning algorithms.Various DLA architectures are proposed and applied to different applications and tasks.However,for most DLAs,their programming interfaces are either difficult to use or not efficient enough.Most DLAs require programmers to directly write instructions,which is time-consuming and error-prone.Another prevailing programming interface for DLAs is high-performance libraries and deep learning frameworks,which are easy to be used and very friendly to users,but their high abstraction level limits their control capacity over the hardware resources thus compromises the efficiency of the accelerator.A design of the programming interface is for DLAs.First various existing DLAs and their programming methods are analyzed and a methodology for designing programming interface for DLAs is proposed,which is a high-level assembly language(called DLA-AL),assembler and runtime for DLAs.DLA-AL is composed of a low-level assembly language and a set of high-level blocks.It allows experienced experts to fully exploit the potential of DLAs and achieve near-optimal performance.Meanwhile,by using DLA-AL,end-users who have little knowledge of the hardware are able to develop deep learning algorithms on DLAs spending minimal programming efforts. | 兰慧盈 Wu Linyang Han Dong Du Zidong | 2019 | High Technology Letters2019，25，4： | 1 |
| 4 | Cambricon-QR:a sparse and bitwise reproducible quantized training accelerator显示文摘Quantized training has been proven to be a prominent method to achieve deep neural network training under limited computational resources.It uses low bit-width arithmetics with a proper scaling factor to achieve negligible accuracy loss.Cambricon-Q is the ASIC design proposed to efficiently support quantized training,and achieves significant performance improvement.However,there are still two caveats in the design.First,Cambricon-Q with different hardware specifications may lead to different numerical errors,resulting in non-reproducible behaviors which may become a major concern in critical applications.Second,Cambricon-Q cannot leverage data sparsity,where considerable cycles could still be squeezed out.To address the caveats,the acceleration core of Cambricon-Q is redesigned to support fine-grained irregular data processing.The new design not only enables acceleration on sparse data,but also enables performing local dynamic quantization by contiguous value ranges(which is hardware independent),instead of contiguous addresses(which is dependent on hardware factors).Experimental results show that the accuracy loss of the method still keeps negligible,and the accelerator achieves 1.61×performance improvement over Cambricon-Q,with about 10%energy increase. | 李楠 ZHAO Yongwei ZHI Tian LIU Chang DU Zidong HU Xing LI Wei ZHANG Xishan LI Ling SUN Guangzhong | 2024 | High Technology Letters2024，30，1： | 0 |
| 5 | Chip design with machine learning:a survey from algorithm perspective显示文摘Chip design with machine learning(ML)has been widely explored to achieve better designs,lower runtime costs,and no human-in-the-loop process.However,with tons of work,there is a lack of clear links between the ML algorithms and the target problems,causing a huge gap in understanding the potential and possibility of ML in future chip design.This paper comprehensively surveys existing studies in chip design with ML from an algorithm perspective.To achieve this goal,we first propose a novel and systematical taxonomy that divides target problems in chip design into three categories.Then,to solve the target problems with ML algorithms,we formulate the three categories as three ML problems correspondingly.Based on the taxonomy,we conduct a comprehensive survey in terms of target problems based on different ML algorithms.Finally,we conclude three key challenges for existing studies and highlight several insights for the future development of chip design with machine learning.By constructing a clear link between chip design problems and ML solutions,we hope the survey can shed light on the road to chip design intelligence from previous chip design automation. | Wenkai HE Xiaqing LI Xinkai SONG Yifan HAO Rui ZHANG Zidong DU Yunji CHEN | 2023 | Science China(Information Sciences)2023，66，11： | 0 |
| 6 | Rescue to the Curse of universality显示文摘From the very beginning of computers,universality has been the core focus in the building of computing machines,such as the universal Turing machine,von Neumann architecture,random-access machines,and universal circuits.Academia has taken universality as the primary principle ever since.However,the Curse of universality,implied from L.G.Valiant's Universal Circuit,states that computers based on logic circuits cannot be both universal and efficient,as the cost of universality isΩ(n log_2 n).Though the Curse has been hidden by the rapid advancement of semiconductor technologies,it has been wielding its effects noticeably in recent years.Due to the ending of Dennard scaling and Moore's law,general-purpose processors leave less room for improvement.Therefore,domain-specific architectures(DSAs),such as deep learning processors,have been exploding,leading to the new golden age of computer architectures.For DSAs,universality is traded off for optimal efficiency.However,we predict that universality will once again be a major concern for post-golden-age computers.In this paper,we discuss how much universality could an efficient computer keep.As a rescue to the Curse,we define and discuss quasi-universal architectures.Quasi-universal architectures can solve any computable problem and are efficient for a wide range of problems.The proposed Recursive-Encapsulated(RE_(NC))architecture achieves maximal universality while keeping optimal efficiency as found in specialized architectures.The discovery of RE_(NC)suggests that current golden-age architectures are not Pareto optimal. | Yongwei ZHAO Zidong DU Qi GUO Zhiwei XU Yunji CHEN | 2023 | Science China(Information Sciences)2023，66，9： | 0 |
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