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| 1 | Mirror image:newfangled cell-level layout technique for single-event transient mitigation显示文摘Recent years,the hardening of combinational circuits is becoming a common concern.Unlike the transistor-level hardening technique,the cell-level hardening technique,a divide and conquer strategy,can substantially make use of some typical character in the cell-circuit module to mitigate single event transient(SET)sensitivity.The mirror image(MI)technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure.3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process,the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25%,and can mitigate the SET pulse width from the posterior-stage PMOS about 10%.The MI technique,a represent of the cell-level technique,may be the future of the hardening of combinational circuits. | Pengcheng Huang Shuming Chen Zhengfa Liang Jianjun Chen Chunmei Hu Yibai He | 2014 | Chinese Science Bulletin2014，59，23： | 4 |
| 2 | Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology显示文摘Heavy ion experiments were performed on D flip-flop(DFF) and TMR flip-flop(TMRFF) fabricated in a 65-nm bulk CMOS process. The experiment results show that TMRFF has about 92% decrease in SEU crosssection compared to the standard DFF design in static test mode. In dynamic test mode, TMRFF shows much stronger frequency dependency than the DFF design, which reduces its advantage over DFF at higher operation frequency. At 160 MHz, the TMRFF is only 3.2× harder than the standard DFF. Such small improvement in the SEU performance of the TMR design may warrant reconsideration for its use in hardening design. | HE YiBai CHEN ShuMing | 2014 | Science China(Information Sciences)2014，57，10： | 3 |
| 3 | Flip-flops soft error rate evaluation approach considering internal single-event transient显示文摘The internal single-event transient(SET) induced upset in flip-flops is becoming significant with the increase of the operating frequency. However, the conventional soft error rate(SER) evaluation approach could only produce an approximate upset prediction result caused by the internal SET. In this paper, we propose an improved SER evaluation approach based on Monte Carlo simulation. A novel SET-based upset model is implemented in the proposed evaluation approach to accurately predict upsets caused by the internal SET. A test chip was fabricated in a commercial 65 nm bulk process to validate the accuracy of the improved SER evaluation approach. The predicted single-event upset cross-sections are consistent with the experimental data. | SONG RuiQiang CHEN ShuMing HE YiBai DU YanKang | 2015 | Science China(Information Sciences)2015，58，6： | 3 |
| 4 | Study on calibration methods of structured light sensor显示文摘 | WANG Baoguang HE Zhonghai LIAO Yibai | 2002 | Chi- nese Journal of Lasers2002，11，3： | 1 |
| 5 | Modeling to predict the time evolution of negative bias temperature instability(NBTI) induced single event transient pulse broadening显示文摘An analytical model is proposed to calculate single event transient (SET) pulse width with bulk complementary metal oxide semiconductor (CMOS) technology based on the physics of semiconductor devices. Combining with the most prevalent negative bias temperature instability (NBTI) degradation model, a novel analytical model is developed to predict the time evolution of the NBTI induced SET broadening in the production, and NBTI experiments and three-dimensional numerical device simulations are used to verify the model. At the same time, an analytical model to predict the time evolution of the NBTI induced SET broadening in the propagation is also proposed, and NBTI experiments and the simulation program with integrated circuit emphasis (SPICE) are used to verify the proposed model. | CHEN ShuMing CHEN JianJun CHI YaQing LIU FanYu HE YiBai | 2012 | Science China(Technological Sciences)2012，55，4： | 0 |
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