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26篇 您的检索式：作者名="Hanumolu"

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	题名	作者	年代	出处	被引量
1	A digital PLL with a stochastic time-to-digital converter 显示文摘	KRATYUK V HANUMOLU P K OK K	2009	IEEE Trans Circ Syst I2009，56，8：	1
2	Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers 显示文摘	WU Ting HANUMOLU P K MAYARAM K	2009	IEEE Journal of Solid-State Circuits2009，44，2：	1
3	A digital PLL with a stochastic time-to-digital converter显示文摘	KRATYUK V HANUMOLU P K OK K	2009	IEEE Transactions on Circuits and Systems I2009，56，8：	1
4	A Digital PLL with a Stochastic Time-to-Digital Converter 显示文摘	Volodymyr Kratyuk Pavan Kumar Hanumolu Kerem Ok	2009	IEEE Transcations on Circuits and Systems 12009，56，8：	1
5	K, Moon U - K,Mayaram K,Fre-quency detector for fast frequency lock of digitalPLLs 显示文摘	Hanumolu P	2007	Electronics Letters2007，43，1：	1
6	Me- thod for a constant loop bandwidth in LC-VCO PLL frequency synthesizers 显示文摘	WU T HANUMOLU P K MAYARAM K	2009	IEEE Journal of Solid-State Circuits2009，44，2：	1
7	Analysis of charge-pump phase-locked loops显示文摘	Hanumolu P K Brownlee M Mayaram K		0，，：	1
8	An 8 × 5 Gb/s parallel receiver with collaborative timing recov- ery显示文摘	Agrawal A Liu A Hanumolu P H	2009	Solid-State Circuits IEEE Journal of2009，24，11：	1
9	Analysis of Charge-Pump Phase- Locked Loops显示文摘	Paean Kumar Hanumolu Merrick Brownlee Kartikeya Mayaram Un-Ku Moon	2004	IEEE Transactions on Circuits and Systems2004，51，9：	1
10	An 8 × 5 Gb/s parallel receiver with collaborative timing recovery 显示文摘	AGRAWAL A LIU A HANUMOLU P K	2009	IEEE J Sol Sta Circ2009，44，11：	1
11	A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked loop analogy显示文摘	Kratyuk Volodymyr Hanumolu Pavan Kumar Moon Un-Ku	2007	IEEE Trans Circuits Syst Ⅱ2007，54，3：	1
12	Analysis of charge-pump phase-locked loops显示文摘	HANUMOLU P BROWNLEE M MAYARAM K	2004	IEEE Transactions on Circuits and Systems-Ⅰ2004，51，9：	1
13	Analysis of charge-pump phase-locked loops 显示文摘	HANUMOLU P K BROWNLEE M MAYARAM K	2004	IEEE Transactions on Circuits and Systems: I2004，51，9：	1
14	Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers 显示文摘	WU T HANUMOLU P K MAYARAM K	2009	IEEE Journal of Solid-State Circuits2009，44，2：	1
15	A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy 显示文摘	KRATYUK V HANUMOLU PK UN-KU MOON	2007	IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs2007，54，3：	1
16	Analysis of Charge-Pump Phase-Locked Loops显示文摘	Hanumolu P K Brownlee M Mayaram K	2004	IEEE Transactions on Circuits and Systems2004，51，9：	1
17	Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers显示文摘	WU T HANUMOLU P K MAYARAM K	2009	IEEE Journal of Solid-State Circuits2009，44，2：	1
18	Low- Power Supply- Regulation Techniques for Ring Oscillators in Phase - Locked Loops Using a Split - Tuned Architecture显示文摘	Arakali A Gondi S Hanumolu P K	2009	IEEE Journal of Solid - State Circuits2009，44，8：	1
19	Method for a constant loop bandwidth in LC-VCO PLL frequency synthesizers显示文摘	Wu T Hanumolu P K Mayaram K		0，，：	1
20	Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers 显示文摘	Wu Ting Hanumolu P K	2009	IEEE Transcations on Solid-State Circuits2009，44，2：	1

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