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| 1 | P3Stor: A parallel, durable flash-based SSD for enterprise-scale storage systems显示文摘Driven by data-intensive applications, flash-based solid state drives (SSDs) have become increasingly popular in enterprise-scale storage systems. Flash memory exhibits inherent parallelism. However, existing solid state drives have not fully exploited this superiority. We propose P3Stor, a parallel solid state storage architecture that makes full use of flash memory by utilizing module- and bus-level parallelisms to increase average bandwidth and employing chip-level interleaving to hide I/O latency. To improve the bandwidth utilization of traditional interface protocols (e.g., SATA), P3Stor adopts PCI-E interface to support concurrent transactions. Based on the proposed parallel architecture, we design a lazy flash translation layer (LazyFTL) to manage the address space. The proposed LazyFTL adopts flexible super page-level mapping scheme to support multi-level parallelisms. It is able to distinguish hot data from cold data, and hot data identification enables LazyFTL to direct hot and cold data to separate physical blocks, which reduces page migrations when reclaiming blocks. As garbage collector migrates fewer valid pages, write amplification is significantly reduced, which in turn helps to extend the life span. Moreover, LazyFTL rarely triggers wear-leveling process. The lazy wear-leveling mechanism protects users' requests from being disrupted by background operations. With the guidance of hot data identification, an intelligent write buffer is used to reduce program operations to flash chips. This is meaningful in extending P3Stor's life span. The performance evaluation using trace-driven simulations and theoretical analysis shows that P3Stor achieves high performance and its life span is more than doubled. | XIAO Nong , CHEN ZhiGuang, LIU Fang, LAI MingChe & AN LongFei Department of Computer Science, National University of Defense Technology, Changsha 410073, China | 2011 | Science China(Information Sciences)2011，54，6： | 7 |
| 2 | A TLP approach for BGP based on local speculation显示文摘With the explosive growth of Internet,the low efficiency of BGP has seriously in-fluenced its usability. In this work,a TLP(thread level parallelism) approach with local speculation is proposed to improve the BGP performance. The thread parti-tion is locally performed on each separated sub-module at route processing,and the speculation strategy is implemented to guarantee the memory consistency and sequential commit. Experiments on Intel Quad-core server show that this approach reaches an average speedup of 1.46 under single peer,multi-peers and route flap-ping. It is also shown that the packet throughput can be improved greatly under multiple sessions by taking advantage of TLP. | GAO Lei GONG ZhengHu LIU YaPing LAI MingChe PENG Wei | 2008 | Science in China(Series F)2008，51，11： | 2 |
| 3 | Co‑packaged optics(CPO):status,challenges,and solutions显示文摘Due to the rise of 5G,IoT,AI,and high-performance computing applications,datacenter trafc has grown at a compound annual growth rate of nearly 30%.Furthermore,nearly three-fourths of the datacenter trafc resides within datacenters.The conventional pluggable optics increases at a much slower rate than that of datacenter trafc.The gap between application requirements and the capability of conventional pluggable optics keeps increasing,a trend that is unsustainable.Copackaged optics(CPO)is a disruptive approach to increasing the interconnecting bandwidth density and energy efciency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics.CPO is widely regarded as a promising solution for future datacenter interconnections,and silicon platform is the most promising platform for large-scale integration.Leading international companies(e.g.,Intel,Broadcom and IBM)have heavily investigated in CPO technology,an inter-disciplinary research feld that involves photonic devices,integrated circuits design,packaging,photonic device modeling,electronic-photonic co-simulation,applications,and standardization.This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform,identify the key challenges,and point out the potential solutions,hoping to encourage collaboration between diferent research felds to accelerate the development of CPO technology. | Min Tan Jiang Xu Siyang Liu Junbo Feng Hua Zhang Chaonan Yao Shixi Chen Hangyu Guo Gengshi Han Zhanhao Wen Bao Chen Yu He Xuqiang Zheng Da Ming Yaowen Tu Qiang Fu Nan Qi Dan Li Li Geng Song Wen Fenghe Yang Huimin He Fengman Liu Haiyun Xue Yuhang Wang Ciyuan Qiu Guangcan Mi Yanbo Li Tianhai Chang Mingche Lai Luo Zhang Qinfen Hao Mengyuan Qin | 2023 | Frontiers of Optoelectronics2023，16，1： | 1 |
| 4 | An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network显示文摘An accurate and highly-efficient analysis approach is crucial for a designer to evaluate the performance of on-chip networks. To this end, the novel M/G/1/N queuing models that capture various blocking phenomenon of the wormhole switching router are presented to compute the average waiting time accurately. With the M/G/1/N queuing models, this paper then presents the performance analysis algorithm to estimate some key metrics in terms of packet latency, buffer utilization, etc. The comparisons with SystemC simulated results show that the proposed approach with mean errors of 6.9% and 7.8% achieves the speedups of 117 and 101 for single-channel and multi-channel routers respectively. In our design methodology, this approach can direct NoC synthesis process effectively and then can be applied to multi-objective optimizations conveniently to find the best mappings. | LAI MingChe GAO Lei XIAO Nong WANG ZhiYing | 2013 | Science China(Information Sciences)2013，56，7： | 1 |
| 5 | A Highly-efficient Approach of Parallel Access to Routing Table on TBGP显示文摘 | GAO Lei LAI Mingche GONG Zhenghu | 2010 | Chinese Journal of Electronics2010，19，1： | 0 |
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