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| 1 | Evolution of MPP SoC architecture techniques显示文摘The evolution of chip architecture is discussed in this paper. Then MPP SoC architectures according to three kinds of computing paradigms are analyzed. Based on these discussions and analyses, array processor architecture for unified change is presented, which could implement the simplification, effectiveness and versatility of both data level and non-data level parallel algorithm's programming. | SHEN XuBang | 2008 | Science in China(Series F)2008，51，6： | 7 |
| 2 | A chaos-based image encryption algorithm using alternate structure显示文摘Combined with two chaotic maps, a novel alternate structure is applied to image cryptosystem. In proposed algorithm, a general cat-map is used for permutation and diffusion, as well as the OCML (one-way coupled map lattice), which is applied for substitution. These two methods are operated alternately in every round of encryption process, where two subkeys employed in different chaotic maps are generated through the masterkey spreading. Decryption has the same structure with the encryption algorithm, but the masterkey in each round should be reversely ordered in decryption. The cryptanalysis shows that the proposed algorithm bears good immunities to many forms of attacks. Moreover, the algorithm features high execution speed and compact program, which is suitable for various software and hardware applications. | ZHANG Yiwei WANG YuMin SHEN XuBang | 2007 | Science in China(Series F)2007，50，3： | 6 |
| 3 | Parallelization of intra prediction algorithm based on array processor显示文摘For the characteristics of intra prediction algorithms, the data dependence and parallelism between intra prediction models are first analyzed. This paper proposes a parallelization method based on dynamic reconfigurable array processors provided by the project team, and uses data level parallel(DLP) algorithms in multi-core units. The experimental results show that Y-component of peak signal to noise ratio(Y-PSNR) is improved about 10 dB and the time is saved 63% compared with high-efficiency video coding(HEVC) test model HM10.0. This method can effectively reduce codec time of the video and reduce computational complexity. | 朱筠 Jiang Lin Shi Pengfei Xie Xiaoyan Shen Xubang | 2019 | High Technology Letters2019，25，1： | 4 |
| 4 | Architecture of a Configurable 2-D Adaptive Filter Used for Small Object Detection and Digital Image Processing显示文摘 | Sang Hongshi Shen Xubang Chen Chaoyang | 2003 | Optical Engineering2003，42，8： | 1 |
| 5 | Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching显示文摘A novel structure for a charge pump circuit is proposed, in which the charge-pump (CP) current can adaptively regulated according to phase-locked loops (PLL) frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0.25 μm 2.5 V complementary metal-oxide-semiconductor (CMOS) mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages. | ZHANG Tao ZOU Xuecheng ZHAO Guangzhou SHEN Xubang | 2006 | Wuhan University Journal of Natural Sciences2006，11，2： | 1 |
| 6 | An AP SoC for a unified architecture显示文摘 | Shen XuBang Zhao CuiHua | | 0，，35： | 1 |
| 7 | An AP SoC for a unified architecture显示文摘An instruction level parallel computing paradigm and a unified architecture for an array processor(AP) on a chip(SoC) are presented in this paper.Here 'APU SoC' is short for 'an AP SoC for the unified architecture'.The MISD/MIMD architecture for instruction level parallel computing is unified with the SIMD architecture for data level parallel computing.As a result,all the computing can be implemented on an APU SoC.The APU SoC offers the rationale of an array structure for development in current technology,yet simplicity for the hardware(chip) and software(program) parallel designs.Just as a single processor chip can replace many function module chips,the APU SoC can replace the single-core/multi-core/many-core CPU chip for TLP computing and the ASIC/ASSP/FPGA/RC device array chip for Operation Level Parallel computing. | SHEN XuBang ZHAO CuiHua | 2010 | Chinese Science Bulletin2010，55，35： | 1 |
| 8 | The Strategy of JTAG Testability Design 显示文摘 | Shen Xubang | 1990 | MINI - MICRO SYSTEMS1990，12，1： | 1 |
| 9 | Reconfigurable implementation ARP based on depth threshold in 3D-HEVC显示文摘Aiming at the high computational complexity and low efficiency of the advanced residual prediction(ARP)algorithm in 3 dimension high-efficiency video coding(3D-HEVC),the relationship between the depth value and ARP is analyzed.A fast ARP algorithm based on the depth value is proposed,which is implemented on the reconfigurable array processor developed by the project team.It uses a reconfigurable method to realize flexible switching between interview-ARP and tem-poral ARP.Experimental results show that while keeping the coding rate and the peak signal-to-noise ratio(PSNR)basically unchanged,the coding time of the six test sequences is reduced by 16.21%on average compared with HTM16.1.In contrast with non-reconfiguration,the average coding time is reduced by 52%,so the computational efficiency is improved. | 朱筠 Zhou Jinna Xie Xiaoyan Jiang Lin Wang Shuxin Shen Xubang | 2021 | High Technology Letters2021，27，4： | 0 |
| 10 | A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse显示文摘A 3.5 times PLL clock frequency multiplier for low voltage different signal (LVDS) driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator (VCO) is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time. | ZHANG Tao ZOU Xuecheng ZHAO Guangzhou SHEN Xubang | 2007 | Wuhan University Journal of Natural Sciences2007，12，3： | 0 |
| 11 | Design and Implementation of Memory Access Fast Switching Structure in Cluster-Based Reconfigurable Array Processor显示文摘Memory access fast switching structures in cluster are studied,and three kinds of fast switching structures( FS,LR2 SS,and LAPS) are proposed. A mixed simulation test bench is constructed and used for statistic of data access delay among these three structures in various cases. Finally these structures are realized on Xilinx FPGA development board and DCT,FFT,SAD,IME,FME,and de-blocking filtering algorithms are mapped onto the structures. Compared with available architectures,our proposed structures have lower data access delay and lower area. | Rui Shan Lin Jiang Junyong Deng Xueting Li Xubang Shen | 2017 | Journal of Beijing Institute of Technology2017，26，4： | 0 |
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