|
|
|
题名
|
作者
|
年代
|
出处
|
被引量
|
| 1 | Factors associated with upstaging in patients preoperatively diagnosed with ductal carcinoma in situ by core needle biopsy显示文摘Objective: Patients preoperatively diagnosed with ductal carcinoma in situ(DCIS) by core needle biopsy(CNB) exhibit a significant risk for upstaging on final pathology, which leads to major concerns of whether axillary staging is required at the primary operation. The present study aimed to identify clinicopathological factors associated with upstaging in patients preoperatively diagnosed with DCIS by CNB.Methods: The present study enrolled 604 patients(cN0 M0) with a preoperative diagnosis of pure DCIS by CNB, who underwent axillary staging between August 2006 and December 2015, at Fudan University Shanghai Cancer Center(Shanghai, China).Predictive factors of upstaging were analyzed retrospectively.Results: Of the 604 patients, 20.03%(n = 121) and 31.95%(n = 193) were upstaged to DCIS with microinvasion(DCISM) and invasive breast cancer(IBC) on final pathology, respectively. Larger tumor size on ultrasonography(> 2 cm) was independently associated with upstaging [odds ratio(OR) 1.558, P = 0.014]. Additionally, patients in lower breast imaging reporting and data system(BI-RADS) categories were less likely to be upstaged(4 B vs. 5: OR 0.435, P = 0.002;4 C vs. 5: OR 0.502, P = 0.001). Overall,axillary metastasis occurred in 6.79%(n = 41) of patients. Among patients with axillary metastasis, 1.38%(4/290), 3.31%(4/121)and 17.10%(33/193) were in the DCIS, DCISM, and IBC groups, respectively.Conclusions: For patients initially diagnosed with DCIS by CNB, larger tumor size on ultrasonography(> 2 cm) and higher BIRADS category were independent predictive factors of upstaging on final pathology. Thus, axillary staging in patients with smaller tumor sizes and lower BI-RADS category may be omitted, with little downstream risk for upstaging. | Jing Si Benlong Yang Rong Guo Naisi Huang Chenlian Quan Linxiaoxi Ma Bingqiu Xiu Yun Cao Yue Tang Linxiao Shen Jiajian Chen Jiong Wu | 2019 | Cancer Biology & Medicine2019，16，2： | 3 |
| 2 | Error suppression techniques for energy-efficient high-resolution SAR ADCs显示文摘The successive approximation register(SAR)is one of the most energy-efficient analog-to-digital converter(ADC)architecture for medium-resolution applications.However,its high energy efficiency quickly diminishes when the target resolution increases.This is because a SAR ADC suffers from several major error source,including the sampling kT/C noise,the comparator noise,and the DAC mismatch.These errors are increasing hard to address in high-resolution SAR ADCs.This paper reviews recent advances on error suppression techniques for SAR ADCs,including the sampling kT/C noise reduction,the noise-shaping(NS)SAR,and the mismatch error shaping(MES).These techniques aim to boost the resolution of SAR ADCs while maintaining their superior energy efficiency. | Jiaxin Liu Xiyuan Tang Linxiao Shen Shaolan Li Zhelu Li Wenjuan Guo Nan Sun | 2020 | Journal of Semiconductors2020，41，11： | 2 |
| 3 | Research progress on low-power artificial intelligence of things(AIoT)chip design显示文摘An artificial intelligence of things(AIoT)chip is a critical hardware component in edge devices that supports data acquisition and processing in the artificial intelligence(AI)era.In this paper,we introduce the architecture and circuit techniques for AIoT systems as well as the design challenges associated with them.To address the design challenges,we describe our design approaches to improve energy efficiency from the standpoints of system architecture,AI computing,and data acquisition circuits.Meanwhile,we present our most recent research progress and state-of-the-art AIoT chip demonstrations at a prestigious conference.Our design techniques improve power and energy efficiency by orders of magnitude on corresponding state of the arts(SOTA),allowing for an advanced AIoT chip design. | Le YE Zhixuan WANG Tianyu JIA Yufei MA Linxiao SHEN Yihan ZHANG Heyi LI Peiyu CHEN Meng WU Ying LIU Yiqi JING Hao ZHANG Ru HUANG | 2023 | Science China(Information Sciences)2023，66，10： | 0 |
| 4 | Post-layout simulation driven analog circuit sizing显示文摘Post-layout simulation provides accurate guidance for analog circuit design,but post-layout performance is hard to be directly optimized at early design stages.Prior work on analog circuit sizing often utilizes pre-layout simulation results as the optimization objective.In this work,we propose a post-layoutsimulation-driven(post-simulation-driven for short)analog circuit sizing framework that directly optimizes the post-layout simulation performance.The framework integrates automated layout generation into the optimization loop of transistor sizing and leverages a coupled Bayesian optimization algorithm to search for the best post-simulation performance.Experimental results demonstrate that our framework can achieve over 20%better post-layout performance in competitive time than manual design and the method that only considers pre-layout optimization. | Xiaohan GAO Haoyi ZHANG Siyuan YE Mingjie LIU David ZPAN Linxiao SHEN Runsheng WANG Yibo LIN Ru HUANG | 2024 | Science China(Information Sciences)2024，67，4： | 0 |
您所在的机构暂未开通此部分的功能，请联系管理员