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| 1 | Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for Fast Arithmetic Circuits显示文摘 | Chang Chip-Hong Gu Jiangmin Zhang Mingyan | 2004 | IEEE Transactions On Circuits And Systems2004，51，10： | 1 |
| 2 | Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits显示文摘 | Chip-Hong Chang Jiangmin Gu Mingyan Zhang | 2004 | IEEE Transactions on Circuits and Systems2004，51，10： | 1 |
| 3 | Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits显示文摘 | Chang Chip-Hong Gu Jiangmin Zhang Mingyan | 2004 | IEEE Transactions on Circuits and Systems2004，51，10： | 1 |
| 4 | Ultra Low-Voltage Low-Power CMOS4-2and5-2Compressors for Fast Arithmetic Circuits显示文摘 | Chang Chip-Hong Gu Jiangmin Zhang Mingyan | 2004 | IEEE Circuits and Systems2004，51，10： | 1 |
| 5 | A Novel Covalent Redundant Binary Booth Encoder显示文摘 | He Yajuan Chang Chip-Hong Gu Jiangmin Fahmy Hossam A H | 2005 | IEEE2005，，： | 1 |
| 6 | A high-efficiency low-voltage class-EPA for IoT applications in sub-1 GHz frequency range显示文摘We present and propose a complete and iterative integrated-circuit and electro-magnetic(EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA.The presented class-E PA consists of the onchip power transistor,the on-chip gate driving circuits,the off-chip tunable LC load network and the off-chip LC ladder low pass filter.The design methodology includes an explicit design equation based circuit components values' analysis and numerical derivation,output power targeted transistor size and low pass filter design,and power efficiency oriented design optimization.The proposed design procedure includes the power efficiency oriented LC network tuning,the detailed circuit/EM co-simulation plan on integrated circuit level,package level and PCB level to ensure an accurate simulation to measurement match and first pass design success.The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply.The LC load network is designed to be off-chip for the purpose of easy tuning and optimization.The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies.The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm.Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%.A harmonics suppression of 44 dBc is achieved,making it suitable for massive deployment of IoT devices. | Chenyi Zhou Zhenghao Lu Jiangmin Gu Xiaopeng Yu | 2017 | Journal of Semiconductors2017，38，10： | 0 |
| 7 | Synaptic transistor with multiple biological functions based on metal-organic frameworks combined with the LIF model of a spiking neural network to recognize temporal information显示文摘Spiking neural networks(SNNs)have immense potential due to their utilization of synaptic plasticity and ability to take advantage of temporal correlation and low power consumption.The leaky integration and firing(LIF)model and spike-timing-dependent plasticity(STDP)are the fundamental components of SNNs.Here,a neural device is first demonstrated by zeolitic imidazolate frameworks(ZIFs)as an essential part of the synaptic transistor to simulate SNNs.Significantly,three kinds of typical functions between neurons,the memory function achieved through the hippocampus,synaptic weight regulation and membrane potential triggered by ion migration,are effectively described through short-term memory/long-term memory(STM/LTM),long-term depression/long-term potentiation(LTD/LTP)and LIF,respectively.Furthermore,the update rule of iteration weight in the backpropagation based on the time interval between presynaptic and postsynaptic pulses is extracted and fitted from the STDP.In addition,the postsynaptic currents of the channel directly connect to the very large scale integration(VLSI)implementation of the LIF mode that can convert high-frequency information into spare pulses based on the threshold of membrane potential.The leaky integrator block,firing/detector block and frequency adaptation block instantaneously release the accumulated voltage to form pulses.Finally,we recode the steadystate visual evoked potentials(SSVEPs)belonging to the electroencephalogram(EEG)with filter characteristics of LIF.SNNs deeply fused by synaptic transistors are designed to recognize the 40 different frequencies of EEG and improve accuracy to 95.1%.This work represents an advanced contribution to brain-like chips and promotes the systematization and diversification of artificial intelligence. | Qinan Wang Chun Zhao Yi Sun Rongxuan Xu Chenran Li Chengbo Wang Wen Liu Jiangmin Gu Yingli Shi Li Yang Xin Tu Hao Gao Zhen Wen | 2023 | Microsystems & Nanoengineering2023，9，4： | 0 |
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