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| 1 | Adder design using a 5-input majority gate in a novel “multilayer gate design paradigm” for quantum dot cellular automata circuits显示文摘This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata(QCA) technology.Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer,except for the parts where multilayer wire crossing was used.In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers.Using a 5-input majority gate in a multilayer,a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm.A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area,the requirement of QCA cells in the design and the input-output delay of the circuit.Over all,the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact. | Rohit Kumar Bahniman Ghosh Shoubhik Gupta | 2015 | Journal of Semiconductors2015，36，4： | 2 |
| 2 | Hetero-gate-dielectric double gate junctionless transistor(HGJLT)with reduced band-to-band tunnelling effects in subthreshold regime显示文摘We propose a hetero-gate-dielectric double gate junctionless transistor(HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling(BTBT) in the sub-threshold region. A junctionless transistor(JLT) is turned off by the depletion of carriers in the highly doped thin channel(device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor(n–p–n BJT for channel JLT) in the lateral direction by the source(emitter), channel(base) and drain(collector) regions in JLT structure in off-state.The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. | Bahniman Ghosh Partha Mondal M.W.Akram Punyasloka Bal Akshay Kumar Salimath | 2014 | Journal of Semiconductors2014，35，6： | 2 |
| 3 | Effects of defects on the electronic properties of WTe_2 armchair nanoribbons显示文摘We have investigated the electronic properties of WTe2 armchair nanoribbons with defects.WTe2 nanoribbons can be categorized depending on the edge structure in two types:armchair and zigzag.WTe2 in its bulk form has an indirect band gap but nanoribbons and nanosheets of WTe2 have direct band gaps.Interestingly,the zigzag nanoribbon is metallic while the armchair nanoribbons are semiconducting.Thus they can find applications in device fabrication.Therefore,it is very important to study the effect of defects on the electronic properties of the armchair nanoribbons as these defects can impair the device properties and characteristics.We have considered defects such as:vacancy,rough edge,wrap,ripple and twist in this work.We report the band gap variation with these defects.We have also studied the change in band gap and total energy with varying degrees of wrap,ripple and twist. | Bahniman Ghosh Abhishek Gupta Bhupesh Bishnoi | 2014 | Journal of Semiconductors2014，35，11： | 2 |
| 4 | A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET显示文摘We propose a heterostructure junctionless tunnel field effect transistor(HJL-TFET) using Al Ga As/Si.In the proposed HJL-TFET,low band gap silicon is used in the source side and higher band gap Al Ga As in the drain side.The whole Al Ga As/Si region is heavily doped n-type.The proposed HJL-TFET uses two isolated gates(named gate,gate1) with two different work functions(gate=4.2eV,gate1=5.2eV respectively).The 2-D nature of HJL-TFET current flow is studied.The proposed structure is simulated in Silvaco with different gate dielectric materials.This structure exhibits a high on current in the range of 1.4106Aμm,the off current remains as low as 9.11014Aμm.So I ON/I OFF ratio of ~108is achieved.Point subthreshold swing has also been reduced to a value of ~41 m V/decade for TiO2 gate material. | Shiromani Balmukund Rahi Bahniman Ghosh Pranav Asthana | 2014 | Journal of Semiconductors2014，35，11： | 2 |
| 5 | Analog performance of double gate junctionless tunnel field effect transistor显示文摘For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor(DG-JLTFET) and the results are compared with the conventional n-type double gate tunnel field effect transistor(DG-TFET) counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance,intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET. | M.W.Akram Bahniman Ghosh | 2014 | Journal of Semiconductors2014，35，7： | 2 |
| 6 | Temperature effect on hetero structure junctionless tunnel FET显示文摘For the first time, we investigate the temperature effect on Al Ga As/Si based hetero-structure junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved subthreshold slope(< 60 m V/decade at 300 K) and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure. | Shiromani Balmukund Rahi Bahniman Ghosh Bhupesh Bishnoi | 2015 | Journal of Semiconductors2015，36，3： | 2 |
| 7 | A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel for ultra low power applications显示文摘We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs(having low leakage)are improved by junctionless TFETs through blending advantages of Junctionless FETs(with high on current). We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an In As channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in I_(OFF) of ~9×10^(16)A/ μm, I_(ON) of ~20 μA/ μm, I_(ON)/I_(OFF) of 2×10^(10), threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for Poly Gate/Hf O_2/In As TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and V_(DD) of 0.2 V. | Pranav Kumar Asthana Yogesh Goswami Bahniman Ghosh | 2016 | Journal of Semiconductors2016，37，5： | 1 |
| 8 | Compact analytical model of double gate junction-less field effect transistor comprising quantum-mechanical effect显示文摘We investigate the quantum-mechanical effects on the electrical properties of the double-gate junctionless field effect transistors. The quantum-mechanical effect, or carrier energy-quantization effects on the threshold voltage, of DG-JLFET are analytically modeled and incorporated in the Duarte et al. model and then verified by TCAD simulation. | Shoubhik Gupta Bahniman Ghosh Shiromani Balmukund Rahi | 2015 | Journal of Semiconductors2015，36，2： | 1 |
| 9 | Performance analysis of STT-RAM with cross shaped free layer using Heusler alloys显示文摘We have investigated the performance of a spin transfer torque random access memory(STT-RAM)cell with a cross shaped Heusler compound based free layer using micromagnetic simulations. We have designed a free layer using a Cobalt based Heusler compound. Simulation results clearly show that the switching time from one state to the other state has been reduced, also it has been found that the critical switching current density(to switch the magnetization of the free layer of the STT RAM cell) is reduced. | Tangudu Bharat Kumar Bahniman Ghosh Bhaskar Awadhiya Ankit Kumar Verma | 2016 | Journal of Semiconductors2016，37，1： | 0 |
| 10 | An ab initio study of strained two-dimensional MoSe_2显示文摘We have studied the electronic properties of molybdenum diselenide(MoSe_2) in both bulk and monolayer(zigzag and armchair) forms using density function theory.The metallic nature of the zigzag MoSe_2(ZMoSe_2)nanoribbon and the semiconducting behavior of the armchair MoSe_2(AMoSe_2) nanoribbon have been explored using a band structure calculated using self-consistent calculations.We have also studied the variation in the bandgap in the presence of a small amount of strain(uniaxial,biaxial).The effect of tensile strain has been investigated and shifts in the conduction band and valance band have been observed with different amounts of applied strain. | Bahniman Ghosh Naval Kishor | 2015 | Journal of Semiconductors2015，36，4： | 0 |
| 11 | Effect of defects on the electronic properties of WS_2 armchair nanoribbon显示文摘We have studied the WS2 armchair nanoribbon with various defects like vacancy, edge roughness, twist,turn and ripple and compared how the bandgap changes due to such defects with the bandgap of a nanoribbon with no defects. Materials like WS2 and other transition metal dichalcogenides(MX2) have a graphene like layered structure with hexagonal rings and have properties that have attracted a lot of interest. Hence it is essential to study the changes in the band structure of the nanoribbon of WS2 due to the inclusion of defects like vacancy, rough edge,wrap, ripple and twist for making any device based on WS2. | Bahniman Ghosh Aayush Gupta | 2015 | Journal of Semiconductors2015，36，1： | 0 |
| 12 | Dynamic threshold voltage operation in Si and SiGe source junctionless tunnel field effect transistor显示文摘We propose a dynamic threshold voltage junctionless tunnel FET(DT-JLTFET) in which the threshold voltage can be dynamically adjusted,resulting in higher ON-current.Through 2D numerical simulations,it is presented that the threshold voltage in the DT-JLTFET can be adjusted by applying a voltage to the adjust gate.The impact of the threshold voltage shift on the overall performance of the device is also studied.A comparison is made between the dynamic threshold voltage characteristics of a silicon JLTFET and a Si0.7Ge0.3 source JLTFET. | Shibir Basak Pranav Kumar Asthana Yogesh Goswami Bahniman Ghosh | 2014 | Journal of Semiconductors2014，35，11： | 0 |
| 13 | Nanoscale Ⅲ-Ⅴ on Si-based junctionless tunnel transistor for EHF band applications显示文摘A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor(SG-JLTFET) has been reported which shows excellent dc characteristics at low power supply operation.This device has a thin uniformly n-type doped channel of GaSb i.e.gallium antimonide which is grown epitaxially over silicon substrate.The DC performance parameters such as I_(on),I_(on)/I_(off),average and point subthreshold slope as well as device parameters for analog applications viz.transconductance g_m,transconductance generation efficiency g_m/I_D,various capacitances and the unity gain frequency f_T are studied using a device simulator.Along with examining its endurance to short channel effects,the performances are also compared with a Silicon Dual Gate Junctionless Tunnel FET(DG-JLTFET).The DC and small signal analog performance reflects that GaSb SG-JLTFET has immense purview for extreme high-frequency and low-power applications. | Yogesh Goswami Pranav Asthana Bahniman Ghosh | 2017 | Journal of Semiconductors2017，38，5： | 0 |
| 14 | Voltage assisted control of spin-transfer nano-oscillators显示文摘The spin-transfer nano-oscillator(STNO) has recently acquired a huge amount of research interest, due to its promising easy tunability along with the miniature size. The output frequency control of an STNO through magnetic field and current has been examined almost to its full extent; however, there are issues that still need to be addressed. Here, we propose a novel way of voltage control of the output frequency of an STNO, and alongside reducing its power requirement. | Bahniman Ghosh Gaurav Solanki | 2015 | Journal of Semiconductors2015，36，3： | 0 |
| 15 | P-type double gate junctionless tunnel field effect transistor显示文摘We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor(PDGJLTFET) and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material(TiO2/ of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high ION of 0.3 mA/ m,a low IOFF of 30 fA/ m, a high ION=IOFF ratio of 1 1010, a subthreshold slope(SS) point of 23 mV/decade,and an average SS of 49 mV/decade at a supply voltage of –1 V and at room temperature, which indicates that PDGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits. | M.W.Akram Bahniman Ghosh Punyasloka Bal Partha Mondal | 2014 | Journal of Semiconductors2014，35，1： | 0 |
| 16 | Monte-Carlo simulation studies of the effect of temperature and diameter variation on spin transport in Ⅱ–Ⅵ semiconductor nanowires显示文摘We have analyzed the spin transport behaviour of four Ⅱ–Ⅵ semiconductor nanowires by simulating spin polarized transport using a semi-classical Monte-Carlo approach. The different scattering mechanisms considered are acoustic phonon scattering, surface roughness scattering, polar optical phonon scattering, and spin flip scattering. The Ⅱ–Ⅵ materials used in our study are CdS, CdSe, ZnO and ZnS. The spin transport behaviour is first studied by varying the temperature(4–500 K) at a fixed diameter of 10 nm and also by varying the diameter(8–12 nm) at a fixed temperature of 300 K. For Ⅱ–Ⅵ compounds, the dominant mechanism is for spin relaxation;D'yakonov Perel and Elliot Yafet have been actively employed in the first order model to simulate the spin transport.The dependence of the spin relaxation length(SRL) on the diameter and temperature has been analyzed. | Sabiq Chishti Bahniman Ghosh Bhupesh Bishnoi | 2015 | Journal of Semiconductors2015，36，2： | 0 |
| 17 | A laterally graded junctionless transistor显示文摘This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to improve the I OFF and I ON/I OFF ratio. The decrease of doping concentration in the lateral direction of the channel region depletes a greater number of charge carriers compared to the uniformly doped channel in the OFF-state,which in turn suppresses the OFF state current flowing through the device without greatly affecting the ON state current. | Punyasloka Bal Bahniman Ghosh Partha Mondal M.W.Akram | 2014 | Journal of Semiconductors2014，35，3： | 0 |
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